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Two Methods for Linearity Improvement in Digitally Controlled Delay Elements: Current Starved Type

Document Type : Review Article

Authors

1 Electrical Engineering Department, Mashhad, Iran

2 Engineering Department, Mashhad, Iran

Abstract

Current starved delay elements (CSDEs) are among the popular architectures to manipulate rising or falling edges of signals in order to meet timing requirements. The digitally controllable generations of these topologies are now monotonic and reasonably power efficient, but they lack linearity in full range. Inherently, this subject may not seem problematic because by setting the dimensions of the design elements the desired delay can be acquired. However, in case that a chain of incremental delays are required we tend to employ more linear designs. In this paper two improvements in linearity are examined for two known CS designs. Both of the topologies are in 0.18um technology and meet appropriate design parameters like power, area and monotonic response.

Keywords

References
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Majlesi Journal of Electrical Engineering
Volume 11, Issue 1 - Serial Number 1
March 2017
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