A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology

Ghorbani, Ali; Dolatshahi, Mehdi; Zanjani, S. Mohammadali; Barekatain, Behrang

doi:10.52547/mjee.16.1.65

Document Type : Review Article

Authors

¹ Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran.

² Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran.

³ Big Data Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran.

⁴ Smart Microgrid Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran.

https://doi.org/10.52547/mjee.16.1.65

Abstract

In this paper, a new hybrid low-power and area efficient Carry Look-Ahead Adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed. The proposed CLA design in GDI logic style, not only decreases the circuit area effectively but also decreases the power consumption and delay parameters as well. The proposed design is simulated in HSPICE using the CNFET model parameters. Finally, the simulation results justify a good improvement in the circuit performance parameters such as power consumption, delay, chip size area and power-delay product (PDP) for the proposed CLA circuit.

Keywords

References

[1] Y. S. Mehrabani, R. F. Mirzaee, and M. Eshghi, “A novel low-energy CNFET-based full adder cell using pass-transistor logic,” Int. J. High Perform. Syst. Archit., vol. 5, no. 4, pp. 193–201, 2015.

[2] F. Vasefi and Z. Abid, “Low power N-bit adders and multiplier using lowest-number-of-transistor 1-bit adders,” Can. Conf. Electr. Comput. Eng., vol. 2005, no. May, pp. 1731–1734, 2005.Area-efficient

[3] V. Foroutan, M. Taheri, K. Navi, and A. A. Mazreah, “Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style,” Integr. VLSI J., vol. 47, no. 1, pp. 48–61, 2014.

[4] F. Sharifi, A. Panahi, M. H. Moaiyeri, H. Sharifi, and K. Navi, “High Performance CNFET-based Ternary Full Adders,” IETE J. Res., pp. 1–8, 2017.

[5] M. Mohammadi, M. Mohammadi, and S. Gorgin, “An efficient design of full adder in quantum-dot cellular automata (QCA) technology,” Microelectronics J., vol. 50, pp. 35–43, 2016.

[6] P. Kumar and S. Singh, “Optimization of the area efficiency and robustness of a QCA-based reversible full adder,” J. Comput. Electron., vol. 18, pp. 1478–1489, 2019.

[7] I. Edrisi Arani and A. Rezai, “Novel circuit design of serial–parallel multiplier in quantum-dot cellular automata technology,” J. Comput. Electron., vol. 17, no. 4, pp. 1771–1779, 2018.

[8] M. Sadeghi, K. Navi, and M. Dolatshahi, “A new quantum-dot cellular automata full-adder,” Proc. 2016 5th Int. Conf. Comput. Sci. Netw. Technol. ICCSNT 2016, vol. 41, no. 12, pp. 443–445, 2017.

[9] M. M. Abutaleb, “A new static differential design style for hybrid SET–CMOS logic circuits,” J. Comput. Electron., vol. 14, no. 1, pp. 329–340, 2015.

[10] S. M. A. Zanjani, M. Dousti, and M. Dolatshahi, “A CNTFET universal mixed-mode biquad active filter in subthreshold region,” Int. J. RF Microw. Comput. Eng., vol. 28, no. 9, pp. 1–9, 2018.

[11] S. M. A. Zanjani, M. Dousti, and M. Dolatshahi, “A new low-power, universal, multi-mode Gm-C filter in CNTFET technology,” Microelectronics J., vol. 90, no. March 2018, pp. 342–352, 2019.

[12] H. Taheri Tari, A. Dabaghi Zarandi, and M. R. Reshadinezhad, “Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders,” Microelectron. Eng., 2019.

[13] M. Ghadiry, M. Nadi, H. Mohammadi, and A. Bin Abd Manaf, “Analysis of a novel full adder designed for implementing in carbone nanotube technology,” J. Circuits, Syst. Comput., vol. 21, no. 5, pp. 1–13, 2012.

[14] J. Appenzeller, “Carbon nanotubes for high-performance electronics - Progress and prospect,” Proc. IEEE, vol. 96, no. 2, pp. 201–211, 2008.

[15] S. Lin, Y. Bin Kim, and F. Lombardi, “CNTFET-based design of ternary logic gates and arithmetic circuits,” IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 217–225, 2011.

[16] C. Vudadha, S. P. Parlapalli, and M. B. Srinivas, “Energy efficient design of CNFET-based multi-digit ternary adders,” Microelectronics J., vol. 75, no. February, pp. 75–86, 2018.

[17] R. F. Mirzaee, M. H. Moaiyeri, and K. Navi, “High Speed NP-CMOS and Multi-Output,” vol. 4, no. 3, pp. 531–537, 2010.

[18] M. Bagherizadeh and M. Eshghi, “Two novel low-power and high-speed dynamic carbon nanotube full-adder cells,” Nanoscale Res. Lett., vol. 6, pp. 1–7, 2011.

[19] Z. Abid, H. El-Razouk, and D. A. El-Dib, “Low power multipliers based on new hybrid full adders,” Microelectronics J., vol. 39, no. 12, pp. 1509–1515, 2008.

[20] M. Shoba and R. Nakkeeran, “GDI based full adders for energy efficient arithmetic applications,” Eng. Sci. Technol. an Int. J., vol. 19, no. 1, pp. 485–496, 2016.

[21] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, “Full-swing gate diffusion input logic - Case-study of low-power CLA adder design,” Integr. VLSI J., vol. 47, no. 1, pp. 62–70, 2014.

[22] M. Sarkar, R. Sengupta, A. Basu, D. Das, P. Saswari, and P. Bhattacharjee, “Carry look ahead adder design using CMOS output wired logic based majority gate,” 2017 4th Int. Conf. Opto-Electronics Appl. Opt. Optronix 2017, vol. 2018-Janua, pp. 1–5, 2018.

[23] and R. N. A. Kiani, F. Pourahangaryan, “A Novel CMOS Ripple Comparator Cell Using the Gate-Diffusion Input Technique,” Majlesi J. Electr. Eng., vol. 3, no. 4, pp. 66–71, 2010.

[24] O. Al Badry and M. A. Abdelghany, “Low power 1-Bit full adder using Full-Swing gate diffusion input technique,” Proc. 2018 Int. Conf. Innov. Trends Comput. Eng. ITCE 2018, vol. 2018-March, no. Itce, pp. 205–208, 2018.

[25] M. S. Hossain and F. Arifin, “A Proposed Design of Conventional 4-Bit Carry Look-Ahead Adder Improving Performance,” Proc. - 2020 Adv. Comput. Commun. Technol. High Perform. Appl. ACCTHPA 2020, pp. 89–93, 2020.

[26] J. P. Uyemura, “Arithmetic Circuits in CMOS VLSI,” in Introduction to VLSI Circuits and Systems, 2nd ed., New York, NY: Wiley, 2002, pp. 443–482.

Majlesi Journal of Electrical Engineering

A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology

References

References

Volume 16, Issue 1 - Serial Number 1
March 2022
Pages 65-73

A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology

References

References

Volume 16, Issue 1 - Serial Number 1March 2022Pages 65-73

Volume 16, Issue 1 - Serial Number 1
March 2022
Pages 65-73