[1] Feero, B. Stanley, & P. P. Pande, “Networks-on-chip in a three-dimensional environment: A performance evaluation,” IEEE Transactions on Computers, 2009.
[2] ABBAS, Assad, et al., “A survey on energy-efficient methodologies and architectures of network-on-chip,” Computers & Electrical Engineering, 2014.
[3] MANNA, Kanchan, et al., “Thermal-aware application mapping strategy for network-on-chip based system design,” IEEE Transactions on Computers, 2018.
[4] S. Azampanah, A. Khademzadeh, N. Bagherzadeh, M. Janidarmian, & R. Shojaee, “Contention-aware selection strategy for application-specific network-on-chip,” IET Computers & Digital Techniques, 2013.
[5] S. Forghani, N. Habibi, & M. Firoozbakht, “Network security metric based on attack duration,” In 2015 2nd IEEE International Conference on Knowledge-Based Engineering and Innovation (KBEI), 2015.
[6] A. More, V. Pano, & B. Taskin, “Vertical Arbitration-Free 3-D NoCs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.
[7] R. K. Saini, & M. Ahmed, “2D hexagonal mesh Vs 3D mesh network on chip: A performance evaluation,” International Journal of Computing and Digital Systems, 2015.
[8] M. D. Schatz, R. A. Van de Geijn, & J. Poulson, “Parallel matrix multiplication: A systematic journey,” SIAM Journal on Scientific Computing, 2016.
[9] R. Dash, A. Majumdar, V. Pangracious, A. K. Turuk, & J. L. Risco-Martin, “ATAR: An Adaptive Thermal-Aware Routing Algorithm for 3-D Network-on-Chip Systems,” IEEE Transactions on Components, Packaging and Manufacturing Technology, 2018.
[10] R. Sabbaghi-Nadooshan, M. Modarressi, & H. Sarbazi-Azad, “A Novel De Bruijn Based Mesh Topology for Networks-on-Chip,” In VLSI. IntechOpen, BoD–Books on Demand, 2010.
[11] Y. Chen, J. Hu, X. Ling, & T. Huang, “A novel 3D NoC architecture based on De Bruijn graph,” Computers & Electrical Engineering, 2012.
[12] W. Gao, & P. Zhou, “Customized high performance and energy efficient communication networks for AI chips,” IEEE Access, 2019.
[13] R. Poovendran, & S. Sumathi, “An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design,” Concurrency and computation: practice and experience, 2019.
[14] N. Viswanathan, K. Paramasivam, & K. omasundaram, “Exploring Hierarchical, Cluster based 3D Topologies for 3D NoC,” Procedia Engineering, 2012.
[15] A. Touzene, “On all-to-all broadcast in dense Gaussian network on-chip,” IEEE Transactions on Parallel and Distributed Systems, 2015.
[16] I. Pires, M. Alves, & L. Albini, “Expansible Network-on-Chip Architecture,” Advances in Electrical and Computer Engineering, 2018.
[17] P. Yang, & Q. Wang, “Heterogeneous honeycomb-like NoC topology and routing based on communication division,” International Journal of Future Generation Communication and Networking, 2015.
[18] P. Lotfi-Kamran, A. M. Rahmani, M. Daneshtalab, A. Afzali-Kusha, & Z. Navabi, “EDXY–A low cost congestion-aware routing algorithm for network-on-chips,” Journal of Systems Architecture, 2010.
[19] N. Viswanathan, K. Paramasivam, & K. Somasundaram, “Performance and Cost Metrics Analysis of a 3D NoC Topology using Network Calculus,” Applied Mathematical Sciences, 2013.
[20] A. Ahmadinia, & A. Shahrabi, “A highly adaptive and efficient router architecture for network-on-chip,” The Computer Journal, 2011.
[21] D. Demirbas, I. Akturk, O. Ozturk, & U. Güdükbay, “Application-specific heterogeneous network-on-chip design,” The Computer Journal, 2014.
[22] S. E. Bae, T. W. Shinn, & T. Takaoka, “A faster parallel algorithm for matrix multiplication on a mesh array,” Procedia Computer Science, 2014.
[23] M. Hosseinabady, M. R. Kakoee, J. Mathew, & D. K. Pradhan, “Low latency and energy efficient scalable architecture for massive NoCs using generalized de Bruijn graph,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011.
[24] O. Collins, F. Pollara, S. Dolinar, & J. Statman, “Wiring Viterbi decoders (splitting de Bruijn graphs),” The Telecommunications and Data Acquisition Progress Report, 1989.
[25] A. Louri, H. & Sung, “An efficient 3D optical implementation of binary de Bruijn networks with applications to massively parallel computing,” In IEEE Proceedings of Second International Workshop on Massively Parallel Processing Using Optical Interconnections, 1995.
[26] M. R. Samatham, & D. K. Pradhan, “The de Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI,” IEEE Transactions on Computers, 1989.
[27] P. Faizian, M. A. Mollah, X. Yuan, Z. Alzaid, S. Pakin, & M. Lang, “Random Regular Graph and Generalized De Bruijn Graph with k-Shortest Path Routing,” IEEE Transactions on Parallel and Distributed Systems, 2018.
[28] D. Hoxha, “Sparse Matrices and Summa Matrix Multiplication Algorithm in STAPL Matrix Framework,” Doctoral dissertation, 2016.
[29] M. Schatz, J. Poulson, & R. van de Geijn, “Parallel Matrix Multiplication: 2D and 3D”, FLAME Working Note No. 62, The University of Texas at Austin, 2012.
[30] Y. S. Yang, H. Deshpande, G. Choi, & P. V. Gratz, “SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.
[31] T. Maqsood, S. Ali, S. U. Malik, & S. Madani, “A.Dynamic task mapping for network-on-chip based systems,” Journal of Systems Architecture, 2015.
[32] N. Jafarzadeh, M. Palesi, A. Khademzadeh, & A. Afzali-Kusha, “Data encoding techniques for reducing energy consumption in network-on-chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014.
[33] H. Matsutani, M. Koibuchi, & H. Amano, “Tightly-coupled multi-layer topologies for 3-D NOCs,” In International Conference on Parallel Processing (ICPP), IEEE, 2007.
[34] K. Hwang, & N. Jotwani, “Advanced Computer Architecture,” 3e. McGraw-Hill Education, 2016.