Document Type : Reseach Article
Authors
1 Department of Electronic, College of Electrical Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran.
2 Department of Electronic, College of Electrical Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran
Abstract
Extremely efficient successor and predecessor circuits are suggested in this article using 4 CNTFETs. They have much less interconnections and complexity compared to the best previous circuits. The proposed circuits are designed by combining digital and analog techniques for the first time. They can be expanded for all MVLs like ternary, quaternary, pentaternary, and so on. The proposed designs for quaternary logic reduce the transistor count from 25 to 4 in comparison with the best previous works. Interestingly, in MVLs with more level logics, this difference will increase dramatically. This advantage leads to low complexity and costs. The accurate operation and great performance of introduced circuits are illustrated and their superiority is proved. Additionally, a quaternary half adder is founded on the presented successor and predecessor. The simulation results, which are acquired by comprehensive simulations utilizing Synopsys HSPICE and the 32 nm plenary CNTFET model of Stanford, show that proposed successor and predecessor circuits with only four transistors work accurately. According to these outcomes, in the proposed half-adder, not only the transistor count reduces 32%, but also it has 40% better PDP and 42.05% better EDP in comparison with the best previous work. Also it is more stable against process variation and robust in a wide range of temperature variation.
Keywords
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