Document Type : Reseach Article
10.57647/j.mjee.2024.1802.33
Abstract
This research paper introduces a modified single DC-sourced multilevel inverter (MLI) consisting of several cells made from a controlled switch, a diode, and a capacitor to generate voltage levels in series connection with the H-bridge. By increasing the number of cells more output voltage levels can be generated in proposition to 2n+3 for symmetrical multilevel inverter (S-MLI) and maximum 2(N+1) +1 for asymmetrical multilevel inverter (A-MLI), where N is the number of connected cells. In this article, the proposed inverter utilizes seven control switches, three power diodes, a DC voltage source, and three floating capacitors to generate nine-level (S-MLI), fifteen-level, and seventeen-level (A MLI) output. By employing a modified single DC source configuration, we achieve a substantial reduction in the number of isolated DC sources and switches required for operation. The reduction in control switches minimizes the requirement of gate driver and protection circuit. This enhancement not only simplifies the circuitry but also enhances the inverter's cost-effectiveness and efficiency. A comparison of proposed and other recently developed single-sourced topologies has been done to show the benefits of the proposed topology. The performance of the proposed modified inverter topology is analyzed through MATLAB/Simulink and validated by a laboratory prototype. Through extensive simulation and analysis, we demonstrate the improved performance, reduced component count, and complexity of the proposed MLI design.
Keywords
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Ind. Electron, 68:pp. 236–247, 2021.
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number of switches.”. IEEE Trans. Power Electron,
36(3):pp. 2505–2509, 2021.
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Press, , 2023.
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945, 2014.
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A. Iqbal, and M. A. Memon. “A new multilevel
inverter topology with reduce switch count.”. IEEE
Access, 7:pp. 58584–58594, 2019.
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novel vector-based pulse-width modulation for cascaded H-bridge multilevel inverters.”. Journal of
Operation and Automation in Power Engineering, 11
(2):pp. 113–121, 2023.
[31] M. Khenar, A. Taghvaie, J. Adabi, , and M. Rezanejad. “Multi-level inverter with combined T-type
and cross-connected modules.”. IET Power Electron,
11(8):pp. 1407–1415, 2018.
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switched-capacitor based nine-level boost inverter
topology with reduced switch count and voltage
stress.”. IEEE Access, 7:pp. 174178–174188, 2019.
[33] H. Vahedi, K. Al-Haddad, Y. Ounejjar, and K. Addoweesh. “Crossover switches cell (CSC): A new
multilevel inverter topology with maximum voltage
levels and minimum DC sources.”. Proc. 39th Annu.
Conf. IEEE Ind. Electron. Soc., :pp. 54–59, 2013.
[34] S. Arazm, H. Vahedi, , and K. Al-Haddad. “NineLevel packed U-Cell (PUC9) inverter topology with
single-dc-source and effective voltage balancing of
auxiliary capacitors.”. Proc. IEEE 28th Int. Symp.
Ind. Electron. (ISIE), :pp. 944–949, 2019.
converter.”. US Patent. US 386743A, 1975.
[2] M. Vijeh, M. Rezanejad, E. Samadaei, and K. Bertilsson. “A general review of multilevel inverters based
on main submodules: Structural point of view.”.
IEEE Trans. Power Electron, 34(10):pp. 9479–9502,
2019.
[3] H. P. Vemuganti, S. Dharmavarapu, S. K. Ganjikunta,
H. M. Suryawanshi, and H. Abu Rub. “A survey on
reduced switch count multilevel inverters.”. IEEE
Open J. Ind. Electron. Soc., Early Access, :pp. 1–1,
2020.
[4] M. Trabelsi, A. N. Alquennah, and H. Vahedi.
“Review on Single-DC-Source Multilevel Inverters:
Voltage Balancing and Control Techniques.”. IEEE
Open Journal of the Industrial Electronics Society, 3:
pp. 711–732, 2020.
[5] N. Tak, S. K. Chattopadhyay, and C. Chakraborty.
“Single-Sourced Double-Stage Multilevel Inverter
for Grid-Connected Solar PV Systems.”. IEEE Open
Journal of the Industrial Electronics Society, 3:pp.
561–581, 2022.
[6] M. A. Hosseinzadeh, M. Sarebanzadeh, C. F. Garcia,
E. Babaei, J. Rodriguez, and R. Kennel. “Reduced
multisource switched-capacitor multilevel inverter
topologies.”. IEEE Transactions on Power Electronics,
37(12):pp. 14647–14666, 2022.
[7] S. C. S. Junior, C. B. Jacobina, E. L. L. Fabricio, ´
and A. S. Felinto. “Asymmetric 49-levels cascaded
MPUC multilevel inverter Fed by a single DC
source.”. IEEE Transactions on Industry Applications,
58(6):pp. 7539–7549, 2022.
[8] Mohammed Y. Marouf, Mohammed K. Fellah, Mohammed Yaichi, and Mohammed F. Benkhoris.
“Control of a back-to-back two-level/five-level grid
connection of a Wnd turbine.”. Majlesi Journal of
Electrical Engineering, 12(3), 2018.
[9] F. Esmaeili, H. R. Koofigar, and H. Qasemi. “A novel
single-phase multilevel high-gain inverter with low
voltage stress. ”. IEEE J. Emerg. Sel. Topics Power
Electron, 10(5):pp. 6084–6092, 2022.
[10] L. Zhang, W. Hong, C. Gao, R. Liu, Q. Yu, and C. Wei.
“Selected harmonic mitigation PWM power matching control strategy for asymmetric cascaded Hbridge multilevel inverter.”. IEEE Journal of Emerging and Selected Topics in Power Electronics, 10(4):
pp. 4059–4072, 2022.
[11] M. A. Hosseinzadeh, M. Sarebanzadeh, E. Babaei,
M. Rivera, and P. Wheeler. “A switched-DC source
sub-module multilevel inverter topology for renewable energy source applications.”. IEEE Access, 9:
pp. 135964–135982, 2021.
[12] A. Akbari, J. Ebrahimi, Y. Jafarian, and A. Bakhshai.
“A multilevel inverter topology with an improved
reliability and a reduced number of components.”.
IEEE Journal of Emerging and Selected Topics in
Power Electronics, 10(1):pp. 553–563, 2022.
[13] A. J. Passos Nascimento et al. “Bidirectional isolated
asymmetrical multilevel inverter.”. IEEE Transactions on Circuits and Systems II: Express Briefs, 70
(1):pp. 151–155, 2023.
[14] R. Shalchi Alishah, D. Nazarpour, S. H. Hosseini, and
M. Sabahi. “New hybrid structure for multilevel
inverter with fewer number of components for highvoltage levels.”. IET Power Electron, 7(1):pp. 96–104,
2014.
[15] W. Lin, J. zeng, J. Hu, and J. Liu. “Hybrid nine-level
boost inverter with simplified control and reduced
active devices.”. IEEE J. Emerg. Sel. Top. Power
Electron, 9:pp. 2038–2050, 2021.
[16] M. Ye, R. Peng, Z. Tong, Z. Chen, and Z. Miao. “A
generalized scheme with linear power balance and
uniform switching loss for asymmetric cascaded
H-bridge multilevel inverters.
[17] L. He, J. Sun, Z. Lin, and B. Cheng. “Capacitorvoltage self-balance seven-level inverter with unequal amplitude carrier-based APOD PWM.”.
IEEE Trans. Power Electron, 36:pp. 14002–14013,
2021.
[18] S. S. Lee, C. S Lim, Y. P. Siwakoti, and K. B. Lee.
“Dual-T-type five-level cascaded multilevel inverter
with double voltage boosting gain.”. IEEE Trans.
Power Electron, 35:pp. 9522–9529, 2020.
[19] T. Muhammad et al. “An adaptive hybrid control of
reduced switch multilevel grid connected inverter
for weak grid applications.”. IEEE Access, 11:pp.
28103–28118, 2023.
[20] Samuel S. Yusufi and Adamu S. Abubakar. “A comprehensive review on grid-forming inverter: potential and future trends.”. Majlesi Journal of Electrical
Engineering, 17(1), 2023. [21] Himanshu N. Chaudhari and Pranav B. Darji.
“Asymmetrical modular multilevel converter (AMMC) with mixed cell sub-modules (SM) for improved DC fault blocking capability and reduced
component count.”. Majlesi Journal of Electrical
Engineering, 17(1), 2023.
[22] M. A. Al-Hitmi, M. R. Hussan, A. Iqbal, and S. Islam. “Symmetric and asymmetric multilevel inverter topologies with reduced device count.”. in
IEEE Access, 11:pp. 5231–5245, 2023.
[23] W. Peng, Q. Ni, X. Qiu, and Y. Ye. “Seven-level
inverter with self-balanced switched-capacitor and
its cascaded extension.”. IEEE Trans. Power Electron,
34:pp. 11889–11896, 2019.
[24] T. Roy and P. K. Sadhu. “A step-up multilevel inverter topology using novel switched capacitor converters with reduced components.”. IEEE Trans.
Ind. Electron, 68:pp. 236–247, 2021.
[25] M. Kim, J. K. Han, and G. W. Moon. “A high step-up
switched capacitor 13-level inverter with reduced
number of switches.”. IEEE Trans. Power Electron,
36(3):pp. 2505–2509, 2021.
[26] E. Davaranhagh, E. Babaei, M. Sabahi, and S. Shahmohamadi. “Implementation of three PWM based
control methods for switched boost inverter.”. Majlesi Journal of Electrical Engineering, Articles in
Press, , 2023.
[27] K. Nallamekala. “Harmonic cancellation technique
of four pole induction motor drive by using phase
shifted carrier space vector PWM technique.”. Majlesi Journal of Electrical Engineering, 12:pp. 21–28,
2018.
[28] A. Matsa, I. Ahmed, and M. A. Chaudhari.
“Optimized space vector pulse-width modulation
technique for a five-level cascaded H-bridge inverter.”. Journal of Power Electronics, 14(5):pp. 937–
945, 2014.
[29] M. D. Siddique, S. Mekhilef, N. M. Shah, A. Sarwar,
A. Iqbal, and M. A. Memon. “A new multilevel
inverter topology with reduce switch count.”. IEEE
Access, 7:pp. 58584–58594, 2019.
[30] T. Qanbari, B. Tousi, and M. Farhadi Kangarlu. “A
novel vector-based pulse-width modulation for cascaded H-bridge multilevel inverters.”. Journal of
Operation and Automation in Power Engineering, 11
(2):pp. 113–121, 2023.
[31] M. Khenar, A. Taghvaie, J. Adabi, , and M. Rezanejad. “Multi-level inverter with combined T-type
and cross-connected modules.”. IET Power Electron,
11(8):pp. 1407–1415, 2018.
[32] M. D. Siddique et al. “A new single phase single
switched-capacitor based nine-level boost inverter
topology with reduced switch count and voltage
stress.”. IEEE Access, 7:pp. 174178–174188, 2019.
[33] H. Vahedi, K. Al-Haddad, Y. Ounejjar, and K. Addoweesh. “Crossover switches cell (CSC): A new
multilevel inverter topology with maximum voltage
levels and minimum DC sources.”. Proc. 39th Annu.
Conf. IEEE Ind. Electron. Soc., :pp. 54–59, 2013.
[34] S. Arazm, H. Vahedi, , and K. Al-Haddad. “NineLevel packed U-Cell (PUC9) inverter topology with
single-dc-source and effective voltage balancing of
auxiliary capacitors.”. Proc. IEEE 28th Int. Symp.
Ind. Electron. (ISIE), :pp. 944–949, 2019.
)