Designing Low Dropout Regulator with Low Settling Time, High Power Supply Rejection and Low Line and Load Regulation

Khanian, Najmeh; Golmakani, Abbas

Document Type : Review Article

Authors

Department of Electrical Engineering, organization Sadjad Institute of Higher Education, Mashhad, Iran

Abstract

Low dropout regulators are one of the most important factures of many portable devices. Thus, consider to the complexity of the circuits and increasing request for portable devices, for increasing battery life and minimizing supply noise, regulators with high efficiency, low output noise and small size is required. In these paper two methods to improve the efficiency of LDO regulators is proposed. First method is increasing gain of error amplifier by using cascode technique, to improve steady-state specification. Second method is using a simple subtractor circuit between error amplifier and pass transistor of LDO regulator to improve power supply rejection, slew-rate and steady-state specification. In addition, both methods are used to achieve area efficiency replacing MIM capacitors with MOS transistor. These low dropout regulators has been simulated in TSMC 0.18μm CMOS process. Simulation results show enhancement settling time, good line and load regulation and power supply compare with others LDO regulators.

Keywords

References

[1] S. Lim, and A. Q. Hung, “Low-Dropout (LDO) Regulator Output Impedance Analysis and Transient Performance Enhancement Circuit” IEEE Conf Applied Power Electronics, pp. 1875-1878, 2010.

[2] D. Chen, L. He, and X. Yan, “A Low-Dropout Regulator With Unconditional Stability and Low Quiescent Current” IEEE International Conf Communications, Circuit and Systems Proceedings, Vol. 4, pp. 2215-2218, 2006.

[3] C. Simpson, LDO Regulator Stability Using Ceramic Output Capacitor, Application not 1482. 2006.

[4] V. Gupta, An Accurate Trimless, High-PSRR, Low-Voltage, CMOS Bandgap Reference IC, Ph.D. dissertation, Georgia Institute of Technology, 2007.

[5] Dallas Semiconductor/Maxim, Appl. Note 898, Selecting LDO linear regulators for cellphone designs:http://www.maximic.com/appnotes.cfm/appnote number/898.

[6] J. M. Ingino, and V.R. von Kaenel, “A 4-GHz Clock System for a High Performance System-on-a-Chip Design,” IEEE J. Solid-State Circuits, Vol. 36, pp. 1693-1698, November 2001.

[7] V. Gupta, and G. A. Rincon-Mora, “A Low Dropout, CMOS Regulator with High PSR Over Wideband Frequencies,” Proc. IEEE Int. Symp. on Circuits and Systems, pp. 4245-4248, Kobe, Japan, 2005.

[8] H. Aminzadeh, R. Lotfi, and K. Mafinejad “Low-Power Design Techniques to Improve Noise and Stability Performance of Low-Dropout Regulators”, Iranian Conference on Electrical Engineering, May 2009.

[9] H.Aminzadeh, R.Lotfi and K.Mafinezhad,”Area-Efficient Low-Dropout Regulators Using MOS Capacitors” IEEE International Symposium on Circuits and Systems, pp.1-4,November 2008.

[10] S. K. Hoon, S. Chen, F. Maloberti, J. Chen, and B. Aravind, "A Low Noise, High Power Supply Rejection Low Dropout Regulator for Wireless System-on-Chip Applications," Proc. IEEE Custom Integrated Circuits Conference, pp.759-762, November 2005.

[11] Z. Qianneg, L. Hongjuan and M. Tan, “ A LDO Regulator With Slew-Rate Enhancement Circuit for Low-Power SOC” electronic Information and Control Engineering (ICEICE), International Conference,pp.32-35, April 2011.

Majlesi Journal of Electrical Engineering

Designing Low Dropout Regulator with Low Settling Time, High Power Supply Rejection and Low Line and Load Regulation

References

References

Volume 7, Issue 1 - Serial Number 1
March 2013

Designing Low Dropout Regulator with Low Settling Time, High Power Supply Rejection and Low Line and Load Regulation

References

References

Volume 7, Issue 1 - Serial Number 1March 2013

Volume 7, Issue 1 - Serial Number 1
March 2013