[1] H. Lee, K. N. Leung, and P. K. T. Mok. "A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation." Solid-State Circuits, IEEE Journal of 38.10 (2003): 1739-1744.
[2] S. S. Chong, and P. K. Chan. "Cross feedforward cascode compensation for low-power three-stage amplifier with large capacitive load."Solid-State Circuits, IEEE Journal of 47.9 (2012): 2227-2234.
[3] A. Mirvakili, and V. J. Koomson. "Passive frequency compensation for high gain-bandwidth and high slew-rate two-stage OTA." Electronics Letters50, no. 9 (2014): 657-659.
[4] M. Figueiredo, R. Santos-Tavares, E. Santin, J. Ferreira, G. Evans, and J. Goes. "A two-stage fully differential inverter-based self-biased CMOS amplifier with high efficiency." Circuits and Systems I: Regular Papers, IEEE Transactions on 58, no. 7 (2011): 1591-1603.
[5] Wang, Stanley BT, Ali M. Niknejad, and R. W. Brodersen. "Design of a sub-mW 960-MHz UWB CMOS LNA." Solid-State Circuits, IEEE Journal of 41, no. 11 (2006): 2449-2456.
[6] M. Gupta, U. Singh, and R. Srivastava. "Bandwidth extension of high compliance current mirror by using compensation methods." Active and Passive Electronic Components 2014 (2014).
[7] Rincon-Mora, Gabriel. "Active capacitor multiplier in Miller-compensated circuits." Solid-State Circuits, IEEE Journal of 35.1 (2000): 26-32
[8] H. Aminzadeh ,D. Mohammad and W. A. Serdijn. "Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers." Microelectronics Journal 44.12 (2013): 1201-1207.
[9] K. N. Leung , and P. K.T. Mok. "Analysis of multistage amplifier-frequency compensation." Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on 48.9 (2001): 1041-1056.
[10] H. Lee, and P. K. T. Mok. "Active-feedback frequency-compensation technique for low-power multistage amplifiers." Solid-State Circuits, IEEE Journal of 38.3 (2003): 511-520.
[11] R..G. H. Eschauzier , L. Kerklaan, and J. H. Huijsing. "A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure."Solid-State Circuits, IEEE Journal of 27.12 (1992): 1709-1717.
[12] B. K. Ahuja ,"An improved frequency compensation technique for CMOS operational amplifiers." Solid-State Circuits, IEEE Journal of 18.6 (1983): 629-633.
[13] P. Hurst, S. Lewis, J. Keane, F. Aram, ,& K. C. Dyer, "Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers." Circuits and Systems I: Regular Papers, IEEE Transactions on 51.2 (2004): 275-285..
[14] Y. B. Kamath, R. G. Meyer, and P. R. Gray. "Relationship between frequency response and settling time of operational amplifiers." Solid-State Circuits, IEEE Journal of 9.6 (1974): 347-352.
[15] M. T. Tan, P. K. Chan, C. K. Lam, and C. W. Ng. "AC-boosting frequency compensation with double pole-zero cancellation for multistage amplifiers."Circuits, Systems and Signal Processing 29, no. 5 (2010): 941-951.
[16] G. Dai, C. Huang, and L. Yang. "A dynamic zero frequency compensation for 3 A NMOS ultra-low dropout regulator." Analog Integrated Circuits and Signal Processing 75, no. 2 (2013): 329-333.
[17] A. S. Sedra& K. C. Smith ,Microelectronic circuits(5th edition,2005 ).Oxford:Oxford university press.