[1] R. R. Schaller, “Moore’s Law: past, present, and future,” IEEE Spectrum, vol. 34, pp. 53-59, 1997.
[2] T. Tsuchiya, Y. Sato, and M. Tomizawa, “Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 45, pp. 1116-1121, 1998.
[3] L. Chang, Y.K.Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.J. King, “Extremely Scaled Silicon Nano-CMOS Devices,” in Proc.2003 IEEE, vol. 91, issue 11, pp. 1860-73.
[4] T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi, and K. Murase, “Ultimately Thin Double-Gate SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 50, pp. 830-838, 2003.
[5] L. Chang, S. Tang, T.J. King, J. Bokor, and C. Hu, “Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs,” International Electron Devices Meeting. pp. 719-722.
[6] D. Hisamoto, W.C.Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E.Anderson, T.J. King, and C. Hu, “FinFET-A Self- Aligned Double-Gate MOSFET Scalable to 20 nm,”. IEEE Transactions on Electron Devices. vol. 47, pp. 2320-25, 2000.
[7] J.Kawa, (2013). The Use of FinFETs in IP Design. Chip Design Magazine: Tools, Technologies and Methodologies.
[8] A. Chandorkar, S. Mande, and H. Iwai, Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method, 2008, Retrieved from DSpace @ IIT Bombay: http://dspace.library.iitb.ac.in/jspui/handle/10054/593.
[9] X. Wu, C.H.Philip Chan, A. Orozco, A. Vazquez, A. Chaudhry, and J.P.Colinge, “Dose radiation effects in FinFETs,” Solid-State Electronics, vol. 50, pp. 287–290, 2006.
[10] S.K.Mohapatra, K.P.Pradhan, D. Singh, and P.K.Sahu, “The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design,” IEEE Transactions on Nanotechnology. vol. 14, pp. 546-554, 2015.
[11] L. Colombo, J.J.Chambers, and H. Niimi,(2007). Gate Dielectric Process Technology for the Sub-1 nm Equivalent Oxide Thickness (EOT) Era. The Electrochemical Society Interface, 16(3), 51-55. Retrieved from https://www.electrochem.org/dl/interface/fal/fal07/fall07_p51-55.pdf.
[12] D. Bhattacharya, and N.K.Jha, “FinFETs: From Devices to Architectures,” Advances in Electronics. Article ID 365689, 21 pages. 2014, doi:10.1155/2014/365689
[13] EE Times. Intel’s FinFETs are less fin and more triangle. (http://www.eetimes.com/electronics-news/4373195/Intel-FinFETs-shape-revealed/).
[14] A. Gaurav, S.S.Gill, and N. Kaur, “Performance Analysis of Rectangular and Trapezoidal TG Bulk FinFETs for 20 nm Gate Length,” Annual IEEE India Conference (INDICON), New Delhi. pp. 1-5, 2015, doi: 10.1109/INDICON.2015.7443422
[15] N. Fasarakis, T.A.Karatsori, A. Tsormpatzoglou, D.H.Tassis, K.Papathanasiou, M.Bucher, G. Ghibaudo, and C.A.Dimitriadis, “Compact Modeling of Nanoscale Trapezoidal FinFETs,” IEEE Transactions on Electron Devices. vol. 61, pp. 324-32, 2014.
[16] N. Kaur, M. Rattan, and S.S.Gill, “Impact of gate oxide thickness and aspect ratio of fin height and fin width on nanoscale tapered FinFETs,” IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore. pp. 1787-1791, 2016.
[17] P.Clarke, Electronics 360. Intel Presents Broadwell CPU, 14nm FinFET Process. [Online] Available:http://electronics360.globalspec.com/article/4469/intel-presents-broadwell-cpu-14nm-finfet-process/.
[18] J. Kennedy, and R. Eberhart, “Particle Swarm Optimization,” in Proc. IEEE International Conference on Neural Networks, Perth, WA, vol. 4, pp. 1942-48, 1995, doi: 10.1109/ICNN.1995.488968
[19] D. Karaboga, and B. Basturk, (2008). “On the performance of artificial bee colony (ABC) algorithm,” Applied Soft Computing, vol.8, pp.687–697, 2008.
[20] X.-S. Yang, and A.H. Gandomi, “Bat algorithm: a novel approach for global engineering optimization,” Engineering Computations, vol.29, pp.464-483, 2012.
[21] X.-S. Yang, “Firefly Algorithms for Multimodal Optimization.” In O. Watanabe, & T. Zeugmann (Eds.), Stochastic Algorithms: Foundations and Applications (SAGA). Lecture Notes in Computer Science, Berlin, Heidelberg: Springer. 5792, 169-178. 2009.
[22] X‐S.Yang, and S. Deb, “Cuckoo search via Levy flights,” World Congress on Nature & Biologically Inspired Computing (NaBIC 2009), pp. 210–214, 2009.
[23] N.S.Grewal, M. Rattan, and M.S.Patterh, (2014). “A Linear Antenna Array Failure Correction with Null Steering using Firefly Algorithm,” Defence Science Journal, vol. 64, pp. 136-142, 2014.
[24] N.S.Grewal, M. Rattan, and M.S.Patterh, (2017) “A linear antenna array failure correction using improved bat algorithm,” International Journal of RF and Microwave Computer- Aided Engineering. https://doi.org/10.1002/mmce.21119
[25] R.Kaur, and M. Rattan, “Optimization of the Return Loss of Differentially Fed Microstrip Patch Antenna Using ANN and Firefly Algorithm,” Wireless Personal Communications, vol. 80, pp. 1547–1556, 2015.
[26] B.S.Dhaliwal, and S.S.Pattnaik, “Performance comparison of bio-inspired optimization algorithms for Sierpinski gasket fractal antenna design,” Neural Computing and Applications, vol. 27, pp. 585-592, 2016.
[27] P. Ong, and S. Kohshelan, (2016). “Performances of Adaptive Cuckoo Search Algorithm in Engineering Optimization,” In P. Vasant, G. Weber, & V. Dieu (Eds.), Handbook of Research on Modern Optimization Algorithms and Applications in Engineering and Economics, Hershey, PA: IGI Global, pp. 676-699. doi:10.4018/978-1-4666-9644-0.ch026
[28] S. Mirjalili, “Moth-flame optimization algorithm: A novel nature-inspired heuristic paradigm,” Knowledge-Based Systems. vol. 89. pp. 228–249, 2015.
[29] Y. Taur, “CMOS design near the limit of scaling,” IBM Journal of Research and Development, vol. 46, pp. 213-222, 2002.
[30] Cogenda User’s Guides [Online] Available: http://www.cogenda.com/article/downloads.
[31] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A physically based mobility model for numerical simulation of nonplanar devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. vol. 7, pp. 1164–71, 1988.
[32] 3D FinFET simulation with Density Gradient (DG) quantum correction model [Online]. Available: http://www.cogenda.com/article/examples#FinFET-dg.
[33] Y. Li, and C.-H. Hwang, Nanoscale Transistors. In G.P., Wiederrecht (Eds.), Handbook of Nanoscale Optics and Electronics, The Netherlands: Elsevier, pp. 167-238, 2010.
[34] A.Abraham, Artificial Neural Networks. In P.A. H. Sydenham & R. Thorn (Eds.), Handbook of Measuring System Design, US: John Wiley & Sons Ltd., 2005.
)