Document Type : Review Article
Authors
Department of Electrical and Computer Engineering, Zanjan University, Zanjan, Iran
Abstract
Side-channel attacks are considered to be the most important problems of modern digital security systems. Today, Differential Power Attack (DPA) is one of the most powerful tools for attacking hardware encryption algorithms in order to discover the correct key of the system. In this work, a new scheme based on randomizing power consumption of a fixed-operation logic gate is proposed. The goal of this method is enhancing the immunity of AES algorithm against DPA. Having a novel topology to randomize the power consumption of each Exclusive-NOR gate, the proposed circuit causes random changes in the overall power consumption of the steps of the algorithm; thus, the correlation between the instantaneous power consumption and the correct key is decreased and the immunity of the AES implementations which the key is injected into their process through Exclusive-NOR gates is extremely increased. The proposed method can be used as a general hardening method in the majority of cryptographic algorithms. The results of theoretical analysis and simulations in 90-nm technology demonstrate the capability of the proposed circuits to strengthen AES against DPA. The CMOS area and power consumption overhead is less than 1%.
Keywords
[1] Katz J, Lindell Y. “Introduction to modern cryptography,” CRC press; 2014 Nov 6.
[2] T. Messerges, E. Dabbish, and R. Sloan, “Examining smart-card security under the threat of power analysis attacks,” IEEE Trans. Comput.,vol. 51, no. 5, pp. 541–552, May 2002.
[3] Biryukov A, Daemen J, Lucks S, Vaudenay S. Topics and Research Directions for Symmetric Cryptography,” In Proceedings of Early Symmetric Crypto workshop, 2017 2017 (p. 4). University of Luxembourg.
[4] Y. Zhang, L. Yang, and J. Chen, “RFID and Sensor Networks: Architectures, Protocols, Security, and Integrations,” (Wireless Networks and Mobile Communications). New York, NY, USA: Taylor & Francis, 2010.
[5] W. Rankl and W. Effing, Smart Card Handbook. New York, NY, USA:Wiley, 2004.
[6] K. Finkenzeller, RFID Handbook: Fundamentals and Applications in Contactless Smart Cards, Radio Frequency Identification and Near-Field Communication, 3rd ed. New York, NY, USA: Wiley, 2010.
[7] P. C. Kocher, J. Jaffe, and B. Jun, “Differential power analysis,” in Proc. 19th Annu. Int. Cryptol. Conf. Adv. Cryptol., 1999, pp. 388–397.
[8] K. Wu, H. Li, T. Chen, and F. Yu, “Electromagnetic analysis on elliptic curve cryptosystems: Measures and counter-measures for smart cards,” in Proc. 3rd Int. Symp. IITA, vol. 1. 2009, pp. 40–43.
[9] B. Gammel, H. Bock, and M. Goessel, “Cryptographic unit and method for operating a crytographic unit,” U.S. Patent 7 694 156, Apr. 6, 2010. J.-S. Coron, “Resistance against differential power analysis for elliptic curve cryptosystems,” in Cryptographic Hardware and Embedded Systems. New York, NY, USA: Springer-Verlag, 1999, pp. 292–302.
[10] J.-S. Coron and L. Goubin, “On Boolean and arithmetic masking against differential power analysis,” in Proc. 2nd Int. Workshop CHES, 2000, pp. 231–237.
[11] H. Qu, J. Xu, and Y. Yan, “A random delay design of processor against power analysis attacks,” in Proc. 10th IEEE ICSICT, Nov. 2010, pp. 254–256.
[12] K. H. Boey, Y. Lu, M. O’Neill, and R. Woods, “Random clock against differential power analysis,” in Proc. IEEE APCCAS, Dec. 2010, pp. 756–759.
[13] M. Joye, P. Paillier, and B. Schoenmakers, “On second-order differential power analysis,” in Proc. 7th Int. Workshop CHES, vol. 3659. Edinburgh, U.K., Aug./Sep. 2005, pp. 293–308.
[14] K. Tiri, M. Akmal, and I. Verbauwhede, “A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards,” in Proc. 28th ESSCIRC, 2002, pp. 403–406.
[15] K. Tiri and I. Verbauwhede, “A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation,” in Proc. Des., Autom. Test Eur. Conf. Exhibit., vol. 1. 2004, pp. 246–251.
[16] D. Hwang et al., “AES-based security coprocessor IC in 0.18-μm CMOS with resistance to differential power analysis side-channel attacks,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 781–792, Apr. 2006.
[17] C. Tokunaga and D. Blaauw, “Securing encryption systems with a switched capacitor current equalizer,” IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 23–31, Jan. 2010.
[18] D. Kamel, M. Renauld, D. Bol, F.-X. Standaert, and D. Flandre, “Analysis of dynamic differential swing limited logic for low-power secure applications,” J. Low Power Electron. Appl., vol. 2, no. 1, pp. 98–126, 2012.
[19] S. Mangard, “Masked dual-rail pre-charge logic: DPA-resistance without routing constraints,” in Proc. 7th Int. Workshop Syst. CHES, 2005, pp. 172–186.
[20] T. Popp, M. Kirschbaum, T. Zefferer, and S. Mangard, “Evaluation of the masked logic style MDPL on a prototype chip,” in CHES (Lecture Notes in Computer Science), vol. 4727, P. Paillier and I. Verbauwhede, Eds. New York, NY, USA: Springer-Verlag, 2007, pp. 81–94.
[21] Clavier C, Coron JS, Dabbous N. "Differential power analysis in the presence of hardware countermeasures,” InCryptographic Hardware and Embedded Systems—CHES 2000 2000 (pp. 13-48). Springer Berlin/Heidelberg.
[22] Lu Y, O'Neill MP, McCanny JV. "FPGA implementation and analysis of random delay insertion countermeasure against DPA,” In ICECE Technology, 2008. FPT 2008. International Conference on 2008 Dec 8 (pp. 201-208). IEEE.
[23] Guilley S, Sauvage L, Flament F, Vong VN, Hoogvorst P, Pacalet R. Evaluation of power constant dual-rail logics countermeasures against DPA with design time security metrics. IEEE Transactions on Computers,” 2010 Sep;59(9):1250-63.
[24] Messerges TS. Using second-order power analysis to attack DPA resistant software,” In International Workshop on Cryptographic Hardware and Embedded Systems 2000 Aug 17 (pp. 238-251). Springer, Berlin, Heidelberg.
[25] Mangard S. Hardware countermeasures against DPA-a statistical analysis of their effectiveness,” In ct-rsa 2004 Feb 10 (Vol. 2964, pp. 222-235).
[26] J. J. A. Fournier, S. Moore, H. Li, R. Mullins, and G. Taylor, “Security Evaluation of Asynchronous Circuits,” Proc. International Workshop on Cryptographic Hardware and Embedded Systems, pp. 125-136, 2003.
[27] K. Tiri, D. Hwang, A. Hodjat, B. C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, “Prototype IC with WDDL and differential routing-DPA sesistance assessment,” Proc. International Workshop on Cryptographic Hardware and Embedded Systems, pp. 354-365, 2005.
[28] Verbauwhede, Ingrid M., and Kris JV Tiri. "Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis." U.S. Patent 7,417,468, issued August 26, 2008.
[29] Bucci M, Giancane L, Luzzi R, Trifiletti A. Three-phase dual-rail pre-charge logic. In CHES 2006 Aug (Vol. 4249, pp. 232-241).
[30] Dichtl M, Golić JD. “High-speed true random number generation with logic gates only,” In International Workshop on Cryptographic Hardware and Embedded Systems 2007 Sep 10 (pp. 45-62). Springer, Berlin, Heidelberg.
[31] T.S. Messerges, E. Dabbish, and R. Sloan, “Investigations of Power Analysis Attacks on Smartcards,” Proc. USENIX Workshop Smartcard Technology, pp. 151-161, 1999.
[32] Popp T, Mangard S. “Masked dual-rail pre-charge logic: DPA-resistance without routing constraints,” In International Workshop on Cryptographic Hardware and Embedded Systems 2005 Aug 29 (pp. 172-186). Springer, Berlin, Heidelberg.
[33] Suzuki D, Saeki M, Ichikawa T. “Random Switching Logic: A Countermeasure against DPA based on Transition Probability,” IACR Cryptology ePrint Archive. 2004 Dec;2004:346.
[34] Fish A, Avital M, Dagan H, Keren O, “Inventors; Bar-Ilan University, assignee. Multi-topology logic gates,” United States patent application US 15/301,409. 2015 Apr 29.
[35] Lumbiarres-Lopez R, Lopez-Garcia M, Canto-Navarro E. “Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks,” IEEE Transactions on Dependable and Secure Computing. 2016 Sep 19.
[36] Moradi A, Poschmann A. “Lightweight Cryptography and DPA Countermeasures: A Survey,” InFinancial Cryptography Workshops 2010 Jan 25 (pp. 68-79).
[37] Tuyls P, Hollmann HD, Van Lint JH, Tolhuizen LM. “XOR-based visual cryptography schemes. Designs, Codes and Cryptography,” 2005 Oct 1;37(1):169-86.
[38] Liu PC, Chang HC, Lee CY. A low overhead DPA countermeasure circuit based on ring oscillators,” IEEE Transactions on Circuits and Systems II: Express Briefs. 2010 Jul;57(7):546-50.
[39] Taur Y, Ning TH. "Fundamentals of modern VLSI devices,” Cambridge university press; 2013 May 2.
[40] Attaran, A. and Mirhassani, M., 2015, July. An embedded low-"overhead PLL-based countermeasure against DPA side channel attack,” In Signals, Circuits and Systems (ISSCS), 2015 International Symposium on (pp. 1-4). IEEE.
[41] C. Tokunaga, D. Blaauw, “Secure AES engine with a local switched-capacitor current equalizer,” In Proceedings of ISSCC Dig. Tech. Papers, pp. 274-275, Feb. 2009.
[42] M. Doulcier-Verdier, et al., “A side-channel and fault-attack resistant AES circuit working on duplicated complemented values, ” In Proceedings of ISSCC Dig. Tech. Papers, pp. 274-275, Feb. 2011.
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