[1] Anton Glaser, History of Binary and Other Nondecimal Numeration, Tomash Publishers, 1981.
[2] Ohkubo N., Suzuki M., Shinbo T. et al., “A 4.4 ns CMOS 54 54-b Multiplier Using Pass-Transistor Multiplexer,” IEEE Journal of Solid-State Circuits, Vol. 30, Issue 3, pp. 251-257 , 1995.
[3] Abu-Khater I.S., Bellaouar A. and Elmasry, M.I., “Circuit Techniques for CMOS Low-Power High-Performance Multipliers,” IEEE Journal of Solid-State Circuits, Vol. 31, Issue 10, pp. 1535-1546 , 1996.
[4] Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Designs, New York, Oxford University Press, 2000.
[5] Andrew D. Booth, “A signed binary multiplication technique,” The Quarterly Journal of Mechanics and Applied Mathematics, Volume IV, Pt. 2, 1951.
[6] C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. on Computers, vol. 13, pp. 14-17, 1964.
[7] L. Dadda, “Some schemes for parallel multipliers,” Alta Frcquetiza, vol. 34, pp. 349-356, 1965.
[8] Wen-Chang Yeh and Chein-Wei Jen, “High-Speed Booth Encoded Parallel Multiplier Design,” IEEE Transactions on Computers, Vol. 49, No. 7, July 2000.
[9] Whitney J. Townsend, Earl E. Swartzlander Jr., Jacob A. Abraham, “A comparison of Dadda and Wallace multiplier delays,” Proceedings of SPIE - The International Society for Optical Engineering, 2003.
[10] D. Naresh and G. Babu Kande, “High Speed Signed multiplier for Digital Signal Processing Applications,” IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE), Vol. 8, Issue 2, pp. 57-61.
[11] K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, A. Shimizu, “A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic,” IEEE Journal of Solid-State Circuits, Volume: 25, Issue: 2, pp. 388-395, Apr 1990.
[12] Hsin-Lei Lin, Chang R.C. and Ming-Tsai Chan, “Design of a Novel Radix-4 Booth Multiplier,” The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 2, pp. 837-840, 2004.
[13] Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo, “Modified Booth Multipliers With a Regular Partial Product Array,” IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 56, No. 5, pp. 404-408, May 2009.
[14] Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, and Keshab K. Parhi, “Design of Low-Error Fixed-Width Modified Booth Multiplier,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 5, pp. 522-531, May 2004.
[15] A. Fathi, S. Azizian, R. Fathi, H.G. Tamar, “Low latency, glitch-free booth encoder-decoder for high speed multipliers,” IEICE Electronics Express, Vol. 9, No. 16, pp. 1335-1341, 2012.
[16] Ravindra P. Rajput, M.N. Shanmukha Swamy, “High speed Modified Booth Encoder multiplier for signed and unsigned numbers,” 14th International Conference on Modelling and Simulation, pp. 649-654, 2012.
[17] A. Fathi, S. Azizian, Kh. Hadidi, A. Khoei, “Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations,” IEICE transactions on electronics, Vol. 95, No. 4, pp. 706-709, 2012.
[18] Vincent P. Heuring, Harry F. Jordon, Computer Systems Design and Architecture, Pearson Education, Singapore, 2003.
[19] Sukhmeet Kaur, Suman, Manpreet Signh Manna, “Implementation of Modified Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2),” Advance in Electronic and Electric Engineering, Vol. 3, No. 6, pp. 683-690, 2013.
[20] Sakshi Rajput, Priya Sharma, Gitanjali, and Garima, “High Speed and Reduced Power - Radix-2 Booth Multiplier,” International Journal of Computational Engineering & Management (IJCEM), Vol. 16, Issue 2, pp. 25-31, March 2013.
[21] Ramya Muralidharan, and Chip-Hong Chang, “Radix-8 Booth Encoded Modulo 2n-1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System,” IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 58, No. 5, pp. 982-993, May 2011.
[22] Ramya Muralidharan, and Chip-Hong Chang, “Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers,” IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 60, No. 11, pp. 2940-1952, Nov 2013.
[23] Honglan Jiang, Jie Han, Fei Qiao, and Fabrizio Lombardi, “Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation,” IEEE Transactions on Computers, Vol. 65, No. 8, pp. 2638-2644, Aug 2016.
[24] Chip-Hong Chang, Jiangmin Gu, and Mingyan Zhang, “Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 51, Issue 10, pp. 1985-1997, 2004.
[25] Amir Fathi, Sarkis Azizian, Khayrollah Hadidi, Abdollah Khoei and Amin Chegeni, “CMOS Implementation of a Fast 4-2 Compressor for Parallel Accumulations,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1476-1479, May 2012.
[26] Amir Fathi, Sarkis Azizian, Khayrollah Hadidi and Abdollah Khoei, “A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations,” IEICE Trans. Electron., Vol. E95-C, No. 4, April 2012.
[27] B. Ramkumar, and Harish M. Kittur, “Low-Power and Area-Efficient Carry Select Adder,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2, pp. 371-375, Feb 2012.
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