High Performance Low Latency 16×16 bit Booth Multiplier using Novel 4-2 Compressor Structure

Rahnamaei, Ali; Kiani Sarkaleh, Azadeh

Document Type : Review Article

Authors

¹ Department of Electrical Engineering, Ardabil Branch, Islamic Azad University, Ardabil, Iran.

² Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.

Abstract

In this article, the design procedure of a low latency Booth multiplier has been proposed. With the help of a novel 4-2 compressor, a high-performance 16×16 bit Booth multiplier has been implemented, which depicts high operating frequency. To achieve this, the proposed 4-2 compressor has been utilized successively in the Partial Product Reduction Tree (PPRT) of the multiplier and by means of radix-4 Booth scheme, the multiplier has been designed. The Partial Product (PP) generation circuitry is also based on the other work published by the authors which enables the designed structure to work at the frequency of 350MHz. The main advantage of the designed compressor is the elimination of the middle stage inverters between cascaded blocks of PPRT which considerably enhances the speed of whole system. Simulation results for TSMC 0.18µm CMOS technology and 1.8V power supply have been demonstrated to confirm the correct operation of proposed 4-2 compressor. According to the results, the achieved delay of the critical path for hard test and high capacitive load, equal to 100fF, is 936ps while a power consumption of 255.15µW has been achieved at the operating frequency of 100MHZ.

Keywords

References

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Majlesi Journal of Electrical Engineering

High Performance Low Latency 16×16 bit Booth Multiplier using Novel 4-2 Compressor Structure

References

References

Volume 14, Issue 2 - Serial Number 2
June 2020
Pages 1-9

High Performance Low Latency 16×16 bit Booth Multiplier using Novel 4-2 Compressor Structure

References

References

Volume 14, Issue 2 - Serial Number 2June 2020Pages 1-9

Volume 14, Issue 2 - Serial Number 2
June 2020
Pages 1-9