A CMOS Low-Power Noise Shaping-Enhanced SMASH ΣΔ Modulator

Fakhraie, Habibeh; Moosazadeh, Tohid; Sabbaghy, Reza; Hassanzadeh, Alireza

doi:10.52547/mjee.16.1.95

Document Type : Review Article

Authors

¹ Department of Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran

² Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University, Niayesh Building, Emam Hasan Blvd, Pounak, Tehran, Iran

³ ECE Department, Shahid Beheshti University, Tehran, Iran

https://doi.org/10.52547/mjee.16.1.95

Abstract

A discrete-time (DT) high-resolution and low-power sturdy multi-stage noise-shaping (SMASH) sigma-delta (ΣΔ) modulator is introduced. It proposes major solution for high-resolution applications relying on M-bit digital input-feedforward (DFF) technique which eliminates a power-hungry analog adder before the stage’s quantizer, decreases number of comparators for quantizer implementation and reduces the swing of the integrator’s output and a 2nd-order noise-coupling (NC) technique realized by few extra analog paths and enhances the noise shaping of the modulator without adding active blocks. The effectiveness of the introduced modulator is supported by the behavioral simulation and extensive mathematical analyses. The proposed modulator along with conventional one is simulated in a 0.18μm CMOS technology. The results indicate an outstanding improvement in dynamic range (DR) and resolution with less complexity.

Keywords

References

[1] A. Morgado, R. del Rio, J. de la Rosa, “Resonation-based cascade Σ∆ modulator for broadband low voltage A/D conversion”. Electron. Lett. Vol. 44, No. 2, pp. 97–99, 2008.

[2] K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi, G.C. Temes, “A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, 98 dB THD, and 79 dB SNDR”. IEEE J. Solid-State Circuits, Vol. 43, No. 12, pp. 2601–2612, 2008.

[3] K. Lee, M.R. Miller, G.C. Temes, “An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and 98 dB THD”. IEEE J. Solid-State Circuits, Vol. 44, No. 8, pp. 2202–2211, 2009.

[4] G.C. Temes, “New architectures for low-power delta-sigma analog-to-digital converter”. in IEEE Asia Pacific Conference on Circuits and Systems, pp. 1–6, 2008.

[5] H. Fakhraie, T. Moosazadeh and et al,” multi-stage sigma-delta modulator based on noise-coupling and digital feed-forward techniques”. Analog Integrated Circuits and Signal Processing, https://doi.org/10.1007/s10470-021-01877-0, 2021.

[6] K.-Y. Nam, S.-M. Lee, D. K. Su, and B. A. Woolley, “A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion,” IEEE J. Solid State Circuits, vol. 40, no. 9, pp. 1855-1864, 2005.

[7] Y. Fujimoto, Y. Kanazawa, P. Lore, and M. Miyamoto, "An 80/100MS/s 76.3/70.1dB SNDR ΣΔ ADC for digital TV receivers," in ISSCC Dig. Tech. Papers, pp. 201-210, Feb 2006.

[8] A. Hamoui, M. Sukhon, and F. Maloberti, "Digitally-enhanced 2nd-order ΣΔ modulator with unity-gain signal transfer function," in Proc. IEEE Int. Symp. Circuits Syst., pp. 1664-1667, 2008.

[9] A. Hamoui, M. Sukhon, and F. Maloberti, “ Digitally-enhanced high-order Σ∆ modulators," in Proc. IEEE Int. Conf. Electronics Circuits Syst., pp. 161-170 ,2008.

[10] R. Gaggl, M. Inversi, and A. Wiesbauer, “A power optimized 14-bit SC Σ∆ modulator for ADSL CO applications" in ISSCC Dig. Tech. Papers, pp. 82-83, 2004.

[11] I. Fujimori et al., “A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio”. IEEE J. Solid-State Circuits, Vol. 35, No. 12, pp. 1820–1828, 2000.

[12] L. Bos et al., “Multirate cascaded discrete-time low-pass Σ∆ modulator for GSM/Bluetooth/UMTS,” IEEE J. Solid-State Circuits, Vol. 45, No. 6, pp. 1198–1208, 2010.

[13] N. Maghari, S. Kwon, and U.-K. Moon, “74 dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35 dB open-loop opamp gain,” IEEE J. Solid-State Circuits, Vol. 44, No. 8, pp. 2212–2221, 2009.

[14] M. Taghizadeh and S. Sadughi, “Improved unity-STF sturdy MASH Σ∆ modulator for low-power wideband applications,” Electron. Lett., Vol. 51, No. 23, pp. 1941–1942, Nov. 2015.

[15] B. Khazaeili, M. Yavari. "MASH ΣΔ modulator with highly reduced in‐band quantization noise", Electronics Letters, 2014.

[16] C. Han and N. Maghari, “Delay based noise cancelling sturdy MASH delta-sigma modulator,” Electron. Lett., Vol. 50, No. 5, pp. 351–353, Feb. 2014.

[17] Wang, Y., and Temes, G.C. “SD ADCs with second-order noise-shaping enhancement” . IEEE Int. Midwest Symp. on Circuits and Systems’, pp. 345–348,9 August 2009.

[18] R. Wei, and J. Yu, “Multi-stage sigma-delta ADC with noise-coupling technology”, IEICE Electronics Express, Vol.13, No.23, 1-9, 2016.

[19] Khazaeili. B, Yavari. M,. “A simple structure for MASH Σ∆ modulators with highly reduced in-band quantization Noise”. Springer J Circ Syst Sig Process.;36: pp. 2125–2153, 2017.

[20] R. Baird, T. Fiez, “Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted Averaging”. IEEE Trans. Circuits Syst. II Vol. 42, No. 12, pp. 753–762, 1995.

[21] S. Kwon and U.-K. Moon, "A high-speed delta-sigma modulator with relaxed DEM timing requirement," in Proc. IEEE Int. Symp. Circuits Syst., pp. 733-736, 2007.

[22] M. A. N. Haroun, “Low-Power High-Speed High-Resolution Delta-Sigma Modulators for Digital TV Receiver in nanometer CMOS [dissertation],” Montreal, Canada, Department of Electrical and Computer Engineering McGill University, April 2014.

[23] Sandner. C, Clara. M, Santner. A, Hartig. T, Kuttner. F,. “A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS”. IEEE J. Solid-State Circuits, Vol. 40, No. 7, 1499–1505. 2005.

[24] Rijo Sebastian, Babita Roslind Jose, T. K. Shahana, Jimson Mathew. "A Low-distortion Hardware Efficient MASH Modulator with Enhanced Noise Shaping", Smart Science, 2017.

[25] Razavi. B, “Principles of Data Conversion System Design”. New York: IEEE Press. 1995.

[26] Kobayashi. T, Nogami. K, Shirotori. Fujimoto. T,Y,. “A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture”. IEEE J. Solid-State Circuits, Vol. 28, 1993.

[27] Dessouky. M, Kaiser. A, “Very low-voltage digital-audio ΣΔ modulator with 88-dB dynamic range using local switch bootstrapping”. IEEE J. Solid-State Circuits, Vol. 36, No. 3, 349-355, Mar. 2001.

[28] Kwak Y-S, et al. “A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta–Sigma Modulator Using Source-Follower-Based Integrators”. IEEE Journal of Solid-State Circuits, Vol. 53 , Issue: 10, 2772 – 2782, Oct. 2018.

[29] Aminzadeh. H., “Study of capacitance nonlinearity in nano-scale multi-stage MOSFET-only sigma-delta modulators,” Int. J. Electron. Commun. (AEÜ) 85, pp. 150-158, 2018.

Majlesi Journal of Electrical Engineering

A CMOS Low-Power Noise Shaping-Enhanced SMASH ΣΔ Modulator

References

References

Volume 16, Issue 1 - Serial Number 1
March 2022
Pages 95-108

A CMOS Low-Power Noise Shaping-Enhanced SMASH ΣΔ Modulator

References

References

Volume 16, Issue 1 - Serial Number 1March 2022Pages 95-108

Volume 16, Issue 1 - Serial Number 1
March 2022
Pages 95-108