Ratna Kumari Jogi; Usha Rani Macigi
Abstract
Image fusion is particularly crucial for diagnostic imaging in medical applications such as radiation therapy and image-guided surgeries. Medical image fusion seeks to improve diagnostic accuracy by preserving important characteristics and features from the individual pictures in the combined image. ...
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Image fusion is particularly crucial for diagnostic imaging in medical applications such as radiation therapy and image-guided surgeries. Medical image fusion seeks to improve diagnostic accuracy by preserving important characteristics and features from the individual pictures in the combined image. This study introduces a novel fusion methodology for MRI and CT medical imaging by decomposing the source images as base and detail layers using a novel three-scale decomposition strategy that employs Gaussian and Guided filters. Gaussian curvature directs the guided filtering procedure for each source image. The base layers are fused using the Proposed Grey Wolf Optimization algorithm (PGWO), which contains an objective function designed to maximize entropy, edge strength, and standard deviation. In order to integrate the detail layers, the activity level information is simultaneously determined using the Enhanced Dual Channel PCNN. To evaluate the effectiveness of the proposed method, thirty slices of seven different types of medical images from various sources were analyzed and compared both visually and statistically with existing approaches.According to experimental data, the suggested approach performs better than traditional approaches in terms of both objective metrics and qualitative image quality. Quantitative findings show notable advancements over current techniques: Standard deviation rises from 15.5 to 32.7%, spatial frequency from 38.2 to 70.5%, mutual information from 42.8 to 62.9%, edge strength from 37.4 to 61.9%, structural similarity index from 37.8 to 43.8%, and image entropy from 12 to 18%.
Muhammad Ili Firdaus Mohamad Sa’ad; Rizalafande Che Ismail; Siti Zarina Md Naziri; Mohd Nazrin Md Isa; Ahmad Husni Mohd Shapri
Abstract
Paddy farmers face significant challenges from bird pests, particularly species such as pipits and sparrows, which can reduce yields by up to 70%, especially during the grain-filling stage, leading to substantial economic losses. Traditional pest control methods such as physical barriers, scare tactics, ...
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Paddy farmers face significant challenges from bird pests, particularly species such as pipits and sparrows, which can reduce yields by up to 70%, especially during the grain-filling stage, leading to substantial economic losses. Traditional pest control methods such as physical barriers, scare tactics, and chemical deterrents are often inefficient and labour-intensive. To address this issue, this research develops an artificial intelligence (AI)-based bird detection system to protect paddy fields. The solution involves using a Field-Programmable Gate Array (FPGA)-accelerated object detection model to accurately identify bird activity in real time. The system integrates a notification mechanism via Telegram to alert farmers immediately, enabling swift manual intervention. The research employed the DEtection TRansformer with ResNet-50 backbone (DETRResNet50) model for its precision and high confidence in detection, running on both Central ProcessingUnit (CPU) and FPGA configurations to optimize performance. Results showed significant improvements in latency and frames per second (FPS) when using FPGA acceleration, demonstrating effective real-time bird detection capabilities. The system’s implementation enhanced crop protection, promoted eco-friendly practices, and improved overall farming efficiency by reducing manual surveillance and providing valuable data for long-term pest management strategies. Key quantitative findings revealed that FPGA acceleration improved FPS by over 200% compared to CPU performance.
Mohamad Harris Misran; Maizatul Alice Meor Said; Mohd Azlishah Othman; Siti Normi Zabri; Eliyana Ruslan; Noor Azwan Shairi; Zahriladha Zakaria; Suleiman Aliyu Babale; Mohd Zahid Idris
Abstract
Microwave sensors have grown in popularity in recent years because of their contactless sensing capability, real-time detection capability, measurement, accuracy, ease of manufacture and robustness. They have become one of the primary choices in smart sensing applications. However, some of their key ...
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Microwave sensors have grown in popularity in recent years because of their contactless sensing capability, real-time detection capability, measurement, accuracy, ease of manufacture and robustness. They have become one of the primary choices in smart sensing applications. However, some of their key limitations, such as accuracy, sensitivity, and selectivity, might be regarded as limiting their utilization and application range. Thus, this project proposed to design and develop a high-accuracy microwave sensor for material characterization. This microwave sensor uses a Defected Ground Structure (DGS) to enhance sensor accuracy in determining the dielectric characteristics of the material under test (MUT). The sensor achieved high accuracy with a percentage error of 0.56% to 1.86% for the tested various MUTs, demonstrating reliable precision. The DGS significantly enhances performance, optimizing efficiency and compactness while reducing transmission losses on cost-effective substrates like FR4. Its high Q-factor of 595 enables detecting small dielectric constant variation.
Quang Vinh Truong; Tuan Dat Tieu
Abstract
Designing high-speed 6T SRAM for efficient read and write operations poses a significant challenge for circuit designers. In this paper, we propose a 65 nm 6T SRAM architecture using sense amplifiers and write driver circuits to enhance the read and write performance. The sense amplifier helps the reading ...
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Designing high-speed 6T SRAM for efficient read and write operations poses a significant challenge for circuit designers. In this paper, we propose a 65 nm 6T SRAM architecture using sense amplifiers and write driver circuits to enhance the read and write performance. The sense amplifier helps the reading process go faster and the reading data be more stable. The write driver is designed with a symmetrical structure to reduce the write delay. In addition, the control circuit performs the checking process to synchronize read operations, optimize latency without interruption. The simulation result shows that the read delay and write delay are 58.66 ps and 79.67 ps, respectively. These delays outperform most of the other study.
Nur Syahadah Yusof; Mohamed Fauzi Packeer Mohamed; Muammar Mohamad Isa; Norhawati Ahmad; Khatijah Aisha Yaacob; Mohd Hendra Hairi
Abstract
Researchers have explored various fabrication methods for organic devices to meet the growing demand for printed electronics and wearables. Inkjet printing has been widely used for deposition of solution-processable materials at low temperatures, making it ideal for flexible electronics. However, nozzle ...
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Researchers have explored various fabrication methods for organic devices to meet the growing demand for printed electronics and wearables. Inkjet printing has been widely used for deposition of solution-processable materials at low temperatures, making it ideal for flexible electronics. However, nozzle clogging and strict ink and substrate requirements limit its commercialization for OTFTs. Besides, the practical applications of OTFT devices are limited by their high operating voltages. To address these limitations, this study proposes a simple, solution-based fabrication method for developing low-voltage OTFTs on Silicon substrates. A novel direct-write printing technique was utilized to deposit the source/drain electrodes at temperatures below 150 °C in ambient conditions without experiencing nozzle clogging issues, while a spin-coating method was employed for the deposition of TIPS-pentacene semiconducting and high-k PVP dielectric layers. Remarkably, the fabricated OTFT achieved a channel length of 120 μm with saturation mobility of 4.49×10−1 cm2/Vs, a threshold voltage of −1.5 V, an On/Off current ratio of 108, and a subthreshold swing of 66.8 mV/decade, operating below −5 V. The integration of direct-write printing with a high-k dielectric layer offers a newapproach for fabricating OTFTs and other organic devices at lower temperatures, making it suitable for flexible electronics.
Manibharathee Muniandy; Selvakumar Mariappan; Jagadheswaran Rajendran; Narendra Kumar; Arokia Nathan
Abstract
On-chip inductors are crucial for enhancing the functionality of microelectronic devices, particularly in wireless communication. Still, traditional designs often lead to increased chip size and reduced performance due to their bulkiness and integration challenges. By utilizing an electromagnetic (EM) ...
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On-chip inductors are crucial for enhancing the functionality of microelectronic devices, particularly in wireless communication. Still, traditional designs often lead to increased chip size and reduced performance due to their bulkiness and integration challenges. By utilizing an electromagnetic (EM) simulation tool, this research presents a novel on-chip inductor design optimized for 65 nm CMOS technology, achieving an inductance of 3.2 nH with a Q-factor of 15.31 at 1.7 GHz. The primary contributor to the Q-factor enhancement is the layout optimization techniques, which improve the Q-factor by approximately 21%. Additionally, further improvements in inductance and Q-factor are achieved by integrating Nickel Zinc Cobalt-based ferroelectric liquid materials into the simulation stack-up layer. This material stack-up serves as a secondary contributor, enhancing the magnetic properties of the inductor and increasing the Q-factor to 15.83 whichis an additional 6% improvement over the proposed design. The proposed layout optimization and material innovations demonstrate the potential for achieving higher inductance values and Q-factors, effectively addressing the limitations of conventional methods. The results highlight the feasibility of incorporating advanced materials in on-chip inductor design, paving the way for next-generation RF integrated circuits that meet the growing demands for miniaturization and energy efficiency in modern electronics.
